How does a D-type flip-flop store and transfer a bit on a clock edge?
The rising-edge-triggered D-type flip-flop: how it copies its D input to its Q output on the rising edge of the clock, its use as a data latch and for data transfer, and reading its behaviour from a timing diagram.
A focused answer to WJEC Eduqas GCSE Electronics on the rising-edge-triggered D-type flip-flop, covering how it copies D to Q on the clock edge, its use as a latch and for data transfer, and reading timing diagrams.
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What this topic is asking
WJEC Eduqas wants you to know the rising-edge-triggered D-type flip-flop: how it copies its D input to its Q output on the rising edge of the clock, how it is used as a data latch (a one-bit memory) and for data transfer, and how to read its behaviour from a timing diagram. The D-type is the basic building block of sequential (memory) logic.
What a flip-flop is
The key difference from a logic gate is memory. A logic gate's output is fixed by its present inputs; a flip-flop remembers a value until told to change it. This ability to store a bit is the foundation of counters, registers and any digital circuit that needs to keep track of a state.
The rising-edge-triggered D-type
"Edge-triggered" means it acts only at the instant the clock rises, not while the clock is high. At that edge, whatever D is becomes the new Q; the output takes the opposite value. This precise, once-per-edge updating keeps digital systems synchronised to the clock, which is why nearly all digital circuits use edge-triggered flip-flops.
Latch and data transfer
As a latch, a D-type captures a passing event and holds it until reset, so a brief input is remembered. For data transfer, the flip-flop samples D at each clock edge and outputs it at Q, moving data one stage per clock - the basis of shift registers and of moving data through a digital system in step with the clock. Grouping flip-flops gives a register that handles a whole multi-bit value together.
Reading a timing diagram
Reading a timing diagram is a common exam task. Work edge by edge: at each rising clock edge, read D, set Q to that value, then keep Q flat until the next rising edge. Changes in D that happen between edges have no effect on Q (until the next edge). Drawing Q as a series of flat segments that step only at the rising edges shows you understand edge-triggering.
Try this
Q1. State what a rising-edge-triggered D-type flip-flop does to its output Q on the rising edge of the clock. [1 mark]
- Cue. It copies the value at D to Q.
Q2. State why a D-type flip-flop is described as a sequential, not a combinational, circuit. [1 mark]
- Cue. It has memory: its output depends on past inputs (the stored bit), not only the present inputs.
Exam-style practice questions
Practice questions written in the style of WJEC exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.
Eduqas style3 marksExplain what happens to the output Q of a rising-edge-triggered D-type flip-flop when a clock edge occurs, and what happens between clock edges.Show worked answer →
A Component 2 Explain question on the D-type. On the rising edge of the clock, the flip-flop copies the value at its D input to its Q output (1 mark). Between clock edges the output holds (stores) that value and does not change, even if D changes (2 marks for holding the value and ignoring D between edges). Markers reward copying D to Q on the rising edge and storing the value between edges. A common error is to say Q follows D continuously, which would be a transparent latch, not an edge-triggered flip-flop.
Eduqas style4 marksA rising-edge-triggered D-type flip-flop starts with Q = 0. The D input is 1 for the first two clock pulses then 0. Describe the output Q after each of the first three rising edges, given D is 1, 1, then 0 at those edges.Show worked answer →
A Component 2 timing question. The flip-flop copies D to Q on each rising edge and holds it until the next. At the first rising edge D = 1, so Q becomes 1 (1 mark). At the second rising edge D = 1, so Q stays 1 (1 mark). At the third rising edge D = 0, so Q becomes 0 (1 mark). Between edges Q holds its value (1 mark for stating it does not change between edges). Markers reward Q = 1, 1, 0 after the three edges and that Q is held between edges. A common error is to change Q in the middle of a clock period.
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Sources & how we know this
- WJEC Eduqas GCSE Electronics specification (from 2017) — WJEC Eduqas (2017)