How are D-type flip-flops connected to make a binary counter, and what is its timing diagram?
Building a 1-bit and a 2-bit binary up-counter from rising-edge-triggered D-type flip-flops, how each stage divides the clock frequency by two, and reading the count from a timing diagram.
A focused answer to WJEC Eduqas GCSE Electronics on binary counters, covering building 1-bit and 2-bit counters from D-type flip-flops, how each stage halves the clock frequency, and reading the count from a timing diagram.
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What this topic is asking
WJEC Eduqas wants you to build a 1-bit and a 2-bit binary up-counter from rising-edge-triggered D-type flip-flops, understand how each flip-flop divides the clock frequency by two, and read the count from a timing diagram. This shows how memory elements combine to count clock pulses.
A flip-flop as a toggle (divide-by-two)
The trick is the feedback: with fed to D, each rising edge copies the opposite of the current Q into Q, so Q flips each time. Two clock pulses are needed for Q to go high then low again, so Q's frequency is half the clock's. This single toggling flip-flop is both a divide-by-two circuit and a one-bit binary counter (it counts 0, 1, 0, 1, ...).
The 2-bit binary up-counter
The second flip-flop is driven by the first's output rather than the main clock, so it changes half as often. Reading the two outputs as a binary number QB QA gives the count: 00 is 0, 01 is 1, 10 is 2, 11 is 3. After 11 the counter rolls over to 00. This is a ripple counter, because each stage triggers the next in turn. Adding a third flip-flop gives a 3-bit counter (0 to 7), and so on - flip-flops count from 0 to .
Frequency division and the timing diagram
The counter is also a chain of frequency dividers: QA is the clock divided by two, QB is divided by four, and so on. On a timing diagram, draw the clock at the top, then QA toggling on each clock rising edge (half the frequency), then QB toggling on each QA rising edge (a quarter of the clock frequency). At any instant, the pattern of the outputs spells out the binary number reached. This is why an astable clock feeding a counter produces neatly divided frequencies.
Try this
Q1. State how many different states a 2-bit binary counter has, and the highest decimal number it reaches. [2 marks]
- Cue. Four states (00, 01, 10, 11); the highest number is 3.
Q2. State the frequency of the output of a single divide-by-two flip-flop fed by a clock. [1 mark]
- Cue. Half the clock: .
Exam-style practice questions
Practice questions written in the style of WJEC exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.
Eduqas style3 marksExplain how a single rising-edge-triggered D-type flip-flop can be connected to divide the clock frequency by two.Show worked answer →
A Component 2 Explain question on a divide-by-two stage. Connect the flip-flop's inverted output back to its own D input (1 mark). Now at each rising clock edge the flip-flop copies into Q, so Q toggles (changes state) on every clock pulse (1 mark). Because Q changes once for every two clock edges (one to set, one to clear), the Q output completes one cycle for every two clock cycles, so its frequency is half the clock frequency (1 mark). Markers reward feeding to D, Q toggling each pulse, and the divide-by-two result. A common error is to omit the feedback connection.
Eduqas style4 marksA 2-bit binary up-counter is built from two D-type flip-flops. Starting from 00, list the sequence of outputs (QB QA) for the first four clock pulses and state the highest number it reaches.Show worked answer →
A Component 2 counting question. A 2-bit counter counts in binary: starting at 00, after each clock pulse it advances 00, 01, 10, 11 then back to 00 (2 marks for the correct binary sequence). Reading QB QA, the outputs after pulses are 01, 10, 11, 00 (1 mark for advancing one each pulse). The highest number is 11 in binary, which is 3 in decimal, so a 2-bit counter counts 0 to 3 (four states) before repeating (1 mark). Markers reward the binary sequence, advancing by one each pulse, and the maximum of 3 (11). A common error is to count beyond 11 before resetting.
Related dot points
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Sources & how we know this
- WJEC Eduqas GCSE Electronics specification (from 2017) — WJEC Eduqas (2017)