Sequential logic: the difference from combinational logic, the SR latch, the clocked D-type and JK flip-flops, edge triggering, and the flip-flop as a one-bit memory.

Set, reset, hold (up to 3 marks): an SR latch made from two cross-coupled NOR gates has a Set ($S$) and a Reset ($R$) input and outputs $Q$ and $\overline{Q}$. Setting $S = 1$, $R = 0$ makes $Q = 1$ (set). Setting $S = 0$, $R = 1$ makes $Q = 0$ (reset). With $S = R = 0$ the latch holds its previous state (memory).

Forbidden state (up to 2 marks): $S = R = 1$ is forbidden because it tries to force both outputs to $0$, so $Q$ and $\overline{Q}$ are no longer complementary; worse, when the inputs return to $0$ together the final state is unpredictable (a race), so the output is undefined.

Markers reward the set, reset and hold behaviour, $Q$ and $\overline{Q}$ as complementary outputs, and the forbidden $S = R = 1$ with the reason (non-complementary, unpredictable next state).

D-type (up to 2 marks): a D-type flip-flop copies the value on its D input to the output Q on the active clock edge, and holds it until the next edge. It stores one bit and has no forbidden state.

JK (up to 2 marks): a JK flip-flop has two control inputs J and K. $J=K=0$ holds, $J=1,K=0$ sets, $J=0,K=1$ resets, and $J=K=1$ toggles (the output changes state on each clock edge). It removes the SR forbidden state by defining $J=K=1$ as toggle.

Edge triggering (up to 1 mark): an edge-triggered flip-flop responds only at the instant the clock changes (the rising or falling edge), not while the clock is steady high or low, which makes the timing precise and avoids the latch being transparent.

Markers reward the D-type copying D to Q, the JK four modes including toggle, and edge triggering meaning the flip-flop acts on the clock transition.