Combinational logic design: deriving a Boolean expression from a truth table (sum of products), minimising with Karnaugh maps, and standard building blocks (half and full adders, decoders, encoders, multiplexers).

Sum of products (up to 3 marks): write a product term for each row that outputs $1$. Row $01$ gives $\overline{A} \cdot B$, row $10$ gives $A \cdot \overline{B}$, row $11$ gives $A \cdot B$. The sum of products is $\overline{A} \cdot B + A \cdot \overline{B} + A \cdot B$.

Simplify (up to 3 marks): group $A \cdot \overline{B} + A \cdot B = A(\overline{B} + B) = A$. The expression is now $A + \overline{A} \cdot B$, which by the standard identity $A + \overline{A} \cdot B = A + B$ simplifies to $A + B$ (this is just the OR gate, as expected since only $00$ gives $0$).

Markers reward the correct sum of products from the three "1" rows, the grouping/simplification, and the minimal answer $A + B$.

Half adder (up to 3 marks): a half adder adds two single bits $A$ and $B$, producing a sum and a carry. Sum $S = A \oplus B$ (XOR, the sum bit), and carry $C = A \cdot B$ (AND, the carry out). It cannot accept a carry in from a lower stage.

Full adder (up to 2 marks): a full adder adds three bits, $A$, $B$ and a carry in from the previous stage, producing a sum and a carry out. It is built from two half adders and an OR gate.

Why needed for multi-bit (up to 1 mark): adding numbers with more than one bit produces carries that must ripple from one column to the next, so each stage above the least significant bit must accept a carry in, which only a full adder does.

Markers reward $S = A \oplus B$ and $C = A \cdot B$ for the half adder, the three-input full adder with carry in and out, and the carry-propagation reason.