What logic topics are in WJEC A-Level Electronics?

The logic systems section covers the standard gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) with their truth tables and Boolean expressions, the laws of Boolean algebra including De Morgan's theorems, combinational logic design from a specification using sum-of-products form and Karnaugh-map simplification, the universality of the NAND gate, and sequential logic with the SR latch, the D-type and JK flip-flops, and how they build counters and shift registers.

What is the difference between combinational and sequential logic?

Combinational logic has an output that depends only on the present combination of inputs, with no memory of the past; gates, adders and decoders are combinational. Sequential logic contains memory elements (flip-flops), so its output depends on the present inputs and the stored state. Counters and shift registers are sequential. The defining difference is memory: sequential circuits remember, combinational circuits do not.

Why is the NAND gate called a universal gate?

A NAND gate can be wired to produce every basic function: tying its inputs together makes a NOT, following a NAND with an inverter makes an AND, and by De Morgan a NAND fed with inverted inputs makes an OR. Since AND, OR and NOT are enough to build any logic function, NAND alone is sufficient. The practical benefit is that a whole circuit can be built from one type of chip, which lowers cost and simplifies fault-finding.

How do flip-flops make a counter?

A JK flip-flop with both inputs high toggles, changing state on each clock edge, so its output completes one cycle for every two input pulses and divides the frequency by two. Connecting several toggling flip-flops in series, with each output clocking the next, divides by two at every stage, so $n$ stages divide by $2^n$ and the outputs read the count in binary. Four stages give a divide-by-sixteen counter that counts 0 to 15.

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WJEC A-Level Electronics Logic Systems: gates, Boolean algebra, combinational and sequential logic explained

A deep-dive WJEC A-Level Electronics guide to Logic Systems. Covers the seven logic gates and truth tables, Boolean algebra and De Morgan's theorems, combinational design with sum-of-products and Karnaugh maps, NAND universality, and sequential logic with the SR latch, D-type and JK flip-flops, counters and shift registers.

Generated by Claude Opus 4.815 min readWJECUpdated 2026-06-16

Reviewed by: AI editorial process; not yet individually human-reviewed

Jump to a section

What the logic section demands
Logic gates and Boolean algebra
Combinational logic design
Sequential logic and flip-flops
How the logic section is examined
The topics, dot point by dot point
For the official specification

What the logic section demands

Digital logic is the half of electronics that deals in ones and zeros, and the WJEC specification builds it carefully from single gates to circuits with memory. The topic rewards precise truth tables, confident Boolean manipulation and a clear grasp of the difference between circuits that do and do not remember.

This guide walks through the section in specification order, then sets out the exam patterns WJEC repeats. Each topic has a matching dot-point page with worked exam questions; this overview ties them together.

Logic gates and Boolean algebra

The seven gates are NOT (invert), AND (all high), OR (any high), NAND (inverted AND), NOR (inverted OR), XOR (inputs differ) and XNOR (inputs match). Each has a truth table and a Boolean expression, with the dot for AND, the plus for OR and a bar for NOT. The laws of Boolean algebra, and especially De Morgan's theorems ( $\overline{A \cdot B} = \overline{A} + \overline{B}$ and $\overline{A + B} = \overline{A} \cdot \overline{B}$ ), let you manipulate and simplify expressions and swap freely between AND and OR forms.

Combinational logic design

A combinational circuit's output depends only on its present inputs. To design one you build the truth table, read off a sum-of-products expression, simplify it (algebraically or with a Karnaugh map that groups adjacent ones into the largest power-of-two blocks), and draw the gates. Because the NAND gate is universal, any simplified circuit can be built from NAND gates alone, letting a design use a single chip type.

Sequential logic and flip-flops

Sequential logic adds memory. The SR latch stores one bit; the D-type flip-flop captures its D input on each clock edge; the JK flip-flop can hold, set, reset or, with both inputs high, toggle. Chaining toggling flip-flops divides the clock by two at each stage, building a binary counter ( $n$ stages divide by $2^n$ ), and chaining D-types passes a bit along, building a shift register for serial-to-parallel conversion.

How the logic section is examined

Expect truth tables and Boolean expressions for given gates, De Morgan transformations, derivation and Karnaugh-map simplification of a circuit from a specification (often a majority voter or comparator), explanations of NAND universality, and counter and flip-flop questions on toggling and frequency division. Method marks are generous if you show the truth table and grouping.

The topics, dot point by dot point

Each topic has a dot-point answer page with worked exam questions and cross-links. Browse them from this overview and the subject hub.

For the official specification

WJEC Eduqas publishes the full specification, past papers and mark schemes at eduqas.co.uk. Always revise from the current specification and the board's own past papers, because question style is board-specific.

Sources & how we know this

WJEC Eduqas GCE A-level Electronics specification — WJEC Eduqas (2017)