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How do chained flip-flops count clock pulses and shift data, and how is the count length set?

Counters and shift registers: the ripple (asynchronous) counter, the synchronous counter, modulo-n counting and resetting, and serial and parallel shift registers.

An Eduqas A-Level Electronics answer on counters and shift registers: the ripple (asynchronous) counter built from toggling flip-flops, the synchronous counter clocked together, modulo-n counting by resetting at a chosen count, and serial and parallel shift registers for moving and converting data.

Generated by Claude Opus 4.813 min answerUpdated 2026-06-02

Reviewed by: AI editorial process; not yet individually human-reviewed

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Quick answer

A counter chains toggling flip-flops to count clock pulses in binary; $n$ flip-flops give $2^n$ states (counts $0$ to $2^n - 1$ ). In a ripple (asynchronous) counter only the first flip-flop sees the input clock and each one clocks the next, so the count ripples through with a cumulative propagation delay. In a synchronous counter all flip-flops share one clock and change together, avoiding that delay. A modulo-n counter counts through $n$ states by detecting a chosen count with a gate and using it to reset the flip-flops (a modulo-10 decade counter resets after $9$ ). A shift register is a chain of flip-flops that moves data along on each clock; it can load and read serially (one bit at a time) or in parallel (all bits at once), and so converts between serial and parallel data.

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What this dot point is asking

Eduqas wants you to describe the ripple (asynchronous) counter, the synchronous counter, modulo-n counting by resetting, and serial and parallel shift registers. These are the standard sequential systems built from flip-flops.

The answer

The ripple (asynchronous) counter

The synchronous counter

Modulo-n counting

Shift registers

Finding the modulus and frequency division of a counter

A synchronous counter uses three flip-flops and is reset when it reaches count $6$ ( $110$ ). State its modulus and the frequency of its most significant output relative to a $1.2\ \text{kHz}$ clock.

step 1: Find the modulus

Resetting on detecting count $6$ gives states $0$ to $5$ , so it is a modulo-6 counter (six states per cycle).

step 2: Relate output frequency to the count

The counter completes one full cycle every $6$ clock pulses, so any output that pulses once per cycle has a frequency of $\frac{1}{6}$ of the clock.

step 3: Calculate

$f_\text{out} = \frac{1.2\ \text{kHz}}{6} = 200\ \text{Hz}$ for a once-per-cycle output. (Counters are widely used as frequency dividers in this way.)

Examples in context

Counters and shift registers are everywhere in digital systems: a decade counter drives a digital clock or a frequency counter, a counter divides an oscillator down to a useful timing rate, and a shift register sends data over a single wire, drives a row of LEDs from a few pins, or delays a signal. The same building blocks let a microcontroller project expand its outputs cheaply and time events accurately.

Try this

Q1. State how many states a counter with five flip-flops has. [1 mark]

Cue. $2^5 = 32$ states.

Q2. State the main disadvantage of a ripple counter. [1 mark]

Cue. Cumulative propagation delay (glitches and a limited maximum speed).

Q3. State what a serial-in parallel-out shift register does. [1 mark]

Cue. It receives data one bit at a time and presents the whole word on parallel outputs (serial-to-parallel conversion).

Exam-style practice questions

Practice questions written in the style of WJEC Eduqas exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.

Eduqas 20215 marksA counter is built from four JK flip-flops, each wired to toggle. State the maximum number of states and the highest count it reaches, and explain how it could be made to count modulo 10 (a decade counter).

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Maximum states (up to 2 marks): $n$ flip-flops give $2^n$ states. Four flip-flops give $2^4 = 16$ states, counting from $0000$ ( $0$ ) up to $1111$ (decimal $15$ ).

Modulo 10 (up to 3 marks): to count modulo 10 (states $0$ to $9$ ), detect the count $1010$ (decimal $10$ ) with an AND gate on the appropriate outputs and use it to reset all the flip-flops back to $0000$ . The counter then rolls over after $9$ , giving ten states ( $0$ to $9$ ) per cycle.

Markers reward $2^4 = 16$ states reaching $15$ , and resetting on the detection of count $10$ (decimal) to give a decade (modulo-10) counter.

Eduqas 20195 marksExplain the difference between an asynchronous (ripple) counter and a synchronous counter, giving one disadvantage of the ripple counter.

Show worked answer →

Asynchronous (ripple) counter (up to 2 marks): only the first flip-flop is clocked by the input; each subsequent flip-flop is clocked by the output of the previous one, so the count "ripples" through the chain.

Synchronous counter (up to 2 marks): all the flip-flops share the same clock, so they change state at the same instant; the logic between them sets which ones toggle on each edge.

Disadvantage of ripple (up to 1 mark): because each stage waits for the previous one, there is a cumulative propagation delay, so at high clock speeds the outputs are briefly wrong (glitches) and the maximum counting speed is limited. The synchronous counter avoids this by clocking all stages together.

Markers reward the ripple chain clocking, the common clock of a synchronous counter, and the cumulative propagation-delay disadvantage of the ripple counter.

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Sources & how we know this

Eduqas GCE AS/A Level Electronics specification (A410QS) — WJEC Eduqas (2017)