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How does the von Neumann architecture move an instruction from memory into the processor and carry it out?

The structure and function of the processor: the arithmetic logic unit, control unit, registers (PC, ACC, MAR, MDR, CIR), buses (data, address, control), and the fetch-decode-execute cycle in the von Neumann architecture.

An OCR H446 answer on the structure and function of the processor: the ALU, control unit, the five registers (PC, ACC, MAR, MDR, CIR), the data, address and control buses, and a step-by-step trace of the fetch-decode-execute cycle in the von Neumann architecture.

Generated by Claude Opus 4.813 min answerUpdated 2026-06-02

Reviewed by: AI editorial process; not yet individually human-reviewed

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Quick answer

The processor is built from an arithmetic logic unit (ALU) that does calculations and logic, a control unit (CU) that decodes instructions and sends control signals, and registers, very fast on-chip stores. The five named registers are the Program Counter (PC, address of the next instruction), the Memory Address Register (MAR, address being accessed), the Memory Data Register (MDR, data in transit to or from memory), the Current Instruction Register (CIR, the instruction being decoded) and the Accumulator (ACC, results of the ALU). Three buses connect the processor and memory: the address bus (one-way, carries addresses), the data bus (two-way, carries data and instructions) and the control bus (carries timing and control signals). The fetch-decode-execute cycle copies the PC to the MAR, reads the instruction into the MDR then the CIR, increments the PC, decodes the instruction in the CU, then executes it, using the ACC for any arithmetic.

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What this dot point is asking

OCR wants you to know the components inside the processor (the ALU, the control unit and the registers), the three system buses, and exactly what happens, register by register, on each pass of the fetch-decode-execute cycle in the von Neumann architecture. This is recall plus the ability to trace a single instruction through the cycle.

The answer

Inside the processor

The five registers OCR names

The three buses

The defining feature of the von Neumann architecture is the stored-program concept: instructions and data are held in the same memory and travel on the same bus. This is simpler and cheaper than the Harvard architecture, which uses separate memories and buses for instructions and data (common in microcontrollers and DSPs because instructions and data can be fetched simultaneously). The shared bus creates the von Neumann bottleneck, where the single path between CPU and memory limits throughput.

Trace one ADD instruction through the cycle

A program has an instruction at address 12: ADD 30, meaning "add the contents of memory location 30 to the accumulator". The PC currently holds 12.

step 1: Fetch (address out)

The contents of the PC (12) are copied into the MAR. The address bus carries 12 to memory. The PC is incremented to 13 so the next cycle will fetch the following instruction.

step 2: Fetch (instruction in)

Memory places the instruction at location 12 onto the data bus; it is read into the MDR. The instruction is then copied from the MDR into the CIR.

step 3: Decode

The control unit examines the CIR, splitting it into the opcode (ADD) and the operand (30). It recognises this as an addition that needs the contents of location 30.

step 4: Execute (operand fetch)

The operand address 30 is placed in the MAR, the data at location 30 is read into the MDR, and the ALU adds it to the current value in the ACC.

step 5: Store result

The sum remains in the ACC, ready for the next instruction. The cycle restarts using the PC value 13.

Examples in context

A 32-bit address bus can address $2^{32}$ bytes, which is 4 GiB of directly addressable memory, the reason 32-bit operating systems are capped near 4 GiB. Doubling the data bus width from 32 to 64 bits doubles the bits transferred per memory access, improving throughput for data-heavy workloads. The control bus carries the interrupt request line that lets a device signal the processor mid-cycle, which links to interrupt handling in systems software. OCR often pairs this content with the Little Man Computer model, where the same fetch-decode-execute steps are made concrete.

Try this

Q1. State which register is incremented during the fetch stage and explain why. [2 marks]

Cue. The PC is incremented so that the next cycle fetches the following instruction in sequence.

Q2. A processor has a 16-line address bus. State the maximum number of memory locations it can address. [1 mark]

Cue. $2^{16} = 65\,536$ locations.

Q3. State one difference between the von Neumann and Harvard architectures. [1 mark]

Cue. Von Neumann shares one memory and bus for instructions and data; Harvard uses separate memories and buses, allowing simultaneous instruction and data fetches.

Exam-style practice questions

Practice questions written in the style of OCR exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.

OCR 20196 marksDescribe the role of each of the following registers during the fetch-decode-execute cycle: the Program Counter (PC), the Memory Address Register (MAR), the Memory Data Register (MDR) and the Current Instruction Register (CIR).

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Award one mark for the role and one for the cycle context of each register, up to six.

The PC holds the address of the next instruction to be fetched; it is copied to the MAR at the start of fetch and then incremented so the cycle moves on.

The MAR holds the address currently being read from or written to; the address bus carries its contents to memory.

The MDR holds the data or instruction just transferred to or from memory across the data bus; during fetch the fetched instruction passes from the MDR into the CIR.

The CIR holds the current instruction while the control unit decodes it and coordinates its execution. Markers reward precise wording ("holds the address of the next instruction", not just "counts").

OCR 20214 marksExplain how the width of the address bus and the width of the data bus each affect the performance or capability of a processor.

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Address bus (2 marks): its width sets the number of uniquely addressable memory locations, $2^{n}$ for $n$ lines, so a wider address bus allows more memory to be addressed directly (for example $2^{32}$ locations from 32 lines). It does not by itself make the processor faster.

Data bus (2 marks): its width sets how many bits are transferred in one operation, so a wider data bus moves more data per cycle and increases throughput between the processor and memory. Markers reward linking address width to addressable capacity and data width to the amount transferred per transfer, not confusing the two.

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Sources & how we know this

OCR AS and A Level Computer Science (H046, H446) specification — OCR (2015)