What makes one processor faster than another, and when is a GPU or a multi-core design the right choice?
Factors affecting processor performance (clock speed, number of cores, cache size and type), pipelining, and the characteristics and uses of CISC and RISC processors, multicore and parallel systems, and GPUs.
An OCR H446 answer on what affects processor performance: clock speed, cores and cache, how pipelining overlaps the fetch-decode-execute stages, and the characteristics and uses of CISC versus RISC processors, multicore and parallel systems, and GPUs.
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What this dot point is asking
OCR wants the three classic factors that affect a single processor's performance (clock speed, cores, cache), how pipelining squeezes more throughput from the fetch-decode-execute cycle, and the characteristics and typical uses of CISC and RISC processors, multicore and parallel systems, and GPUs. Expect "explain" and "discuss" questions comparing designs against a workload.
The answer
Factors affecting performance
Pipelining
CISC versus RISC
Parallel systems and GPUs
Examples in context
A laptop CPU might pair four fast cores with 8 MB of shared L3 cache for responsive general use, while its integrated GPU handles parallel graphics work. Smartphones use ARM RISC processors because low power extends battery life. Supercomputers and AI training rigs stack thousands of GPU cores to exploit data parallelism. Pipelining is why modern CPUs complete close to one instruction per cycle on straight-line code, and why branch prediction exists, to avoid flushing the pipeline on every jump.
Try this
Q1. State two factors, other than clock speed, that affect the performance of a single processor. [2 marks]
- Cue. Number of cores and cache size or type (also pipelining, word length, bus width).
Q2. Explain why RISC processors are common in mobile devices. [2 marks]
- Cue. Simple fixed-length instructions pipeline efficiently and the simpler hardware uses less power, extending battery life.
Q3. State what type of task benefits most from a GPU. [1 mark]
- Cue. Highly data-parallel tasks where the same operation is applied to many data items (for example graphics, matrix arithmetic, machine learning).
Exam-style practice questions
Practice questions written in the style of OCR exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.
OCR 20186 marksA games developer is choosing hardware to train a machine-learning model that processes large matrices. Discuss whether a multi-core CPU or a GPU is better suited to this task.Show worked answer →
This is a levels-of-response question; reward a developed comparison reaching a judgement.
A GPU has thousands of simple cores designed for the same operation applied across many data items at once (data parallelism / SIMD), which matches matrix and vector arithmetic where each element is processed identically. A multi-core CPU has a few powerful, general-purpose cores with large caches and complex control, better for varied, branch-heavy tasks and a small number of threads.
Matrix-heavy machine learning is highly parallel and uniform, so the GPU's many cores give far higher throughput; the CPU would underuse its few cores on such regular work. Conclusion: the GPU is better here, though the CPU still coordinates the work and handles non-parallel parts. Top marks need the data-parallel argument explicitly linked to the matrix workload.
OCR 20224 marksExplain how pipelining improves processor performance, and state one situation in which the benefit is reduced.Show worked answer →
Pipelining (3 marks): the fetch, decode and execute stages of different instructions are overlapped so that while one instruction is being executed, the next is being decoded and a third fetched. This keeps each part of the processor busy and increases instruction throughput (more instructions completed per unit time) without raising the clock speed.
Reduced benefit (1 mark): a branch or jump instruction can mean the instructions already fetched are wrong and must be discarded (a pipeline flush/stall), or a later instruction depends on an earlier result (a data hazard). Markers reward "overlapping stages to increase throughput" plus a valid hazard.
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