What does OCR section 1.1 cover?

Section 1.1 covers the components of a computer and their uses: the structure and function of the processor (ALU, control unit, registers, buses) and the fetch-decode-execute cycle, the factors affecting performance and the types of processor (CISC, RISC, multicore, GPU), input, output and storage devices including magnetic, optical and solid-state storage with RAM, ROM and virtual storage, and the role of system and application software including the operating system's memory management, interrupt handling and scheduling.

What are the five registers in the fetch-decode-execute cycle?

The Program Counter (PC) holds the address of the next instruction. The Memory Address Register (MAR) holds the address being accessed. The Memory Data Register (MDR) holds data or an instruction in transit to or from memory. The Current Instruction Register (CIR) holds the instruction being decoded. The Accumulator (ACC) holds the result of ALU operations. During fetch the PC goes to the MAR, the instruction is read into the MDR then the CIR, and the PC is incremented.

How does an interrupt get handled?

A device raises an interrupt on the control bus. At the end of the current fetch-decode-execute cycle the processor checks for interrupts. If a pending interrupt has high enough priority, the processor saves its current state (registers including the PC) onto the stack, loads and runs the matching interrupt service routine, then restores the saved state from the stack so the interrupted program resumes exactly where it stopped.

When is a GPU better than a multi-core CPU?

A GPU is better for highly data-parallel work where the same operation is applied to many data items at once, such as rendering graphics, image processing and machine-learning matrix arithmetic, because it has thousands of simple cores. A multi-core CPU is better for varied, branch-heavy general-purpose tasks with a small number of threads, because its few cores are powerful and have large caches and complex control logic.

How should I revise section 1.1?

Drill the fetch-decode-execute cycle until you can trace any instruction register by register, and learn the role of each register and bus precisely. Practise comparison questions (HDD vs SSD, RISC vs CISC, CPU vs GPU) that reach a justified conclusion, because OCR sets these as extended-response items. Rehearse interrupt handling and a worked scheduling trace (round robin), since the OS section recurs across papers.

EnglandComputer Science

OCR A-Level Computer Science Computer systems and architecture: processors, storage and the OS made exam-ready

A deep-dive OCR H446 guide to Component 01 section 1.1, the components of a computer. Covers processor architecture and the fetch-decode-execute cycle, performance factors and processor types, input, output and storage devices, and the operating system with memory management, interrupts and scheduling, with the exam patterns OCR repeats.

Generated by Claude Opus 4.815 min readH446 1.1Updated 2026-06-02

Reviewed by: AI editorial process; not yet individually human-reviewed

Jump to a section

What this section actually demands
Processor architecture and performance
Storage and software
How this section is examined
Check your knowledge

What this section actually demands

Section 1.1 is the hardware foundation of Component 01. It looks like pure recall, but OCR turns it into applied comparison and tracing: you must trace an instruction through the fetch-decode-execute cycle, justify a storage or processor choice against a scenario, and explain how the operating system manages memory, interrupts and the CPU. The marks reward precise definitions and clear cause-and-effect reasoning.

This guide walks through the topics in order and sets out the exam patterns OCR repeats. Each topic has a matching dot-point page with practice; this overview ties them together.

Processor architecture and performance

Processor architecture and the fetch-decode-execute cycle sets out the ALU (arithmetic and logic), the control unit (decoding and control signals) and the five registers (PC, MAR, MDR, CIR, ACC), connected to memory by the address bus (one-way, capacity $2^{n}$ ), the data bus (two-way) and the control bus. The von Neumann architecture shares one memory and bus for instructions and data; Harvard separates them. You must be able to trace a single instruction step by step.

Processor performance and types covers what makes a processor fast (clock speed, number of cores, cache size and type), how pipelining overlaps the cycle's stages to raise throughput, and the characteristics and uses of CISC versus RISC, multicore and parallel systems, and GPUs. The recurring exam skill is matching a design to a workload: RISC for low-power mobile, GPUs for data-parallel work, multicore for parallelisable tasks.

Storage and software

Input, output and storage devices explains how magnetic (HDD, tape), optical (CD, DVD, Blu-ray) and solid-state (SSD, flash) storage work, their characteristics and uses, the volatile RAM versus non-volatile ROM distinction, and virtual storage. The classic question compares an HDD and an SSD for a scenario.

Systems software and application software covers the operating system's functions, with memory management (paging, segmentation, virtual memory), interrupt handling via the stack and the interrupt service routine, and scheduling algorithms (round robin, first come first served, shortest job first, multilevel feedback queues), plus the difference between systems software (OS, utilities) and application software.

How this section is examined

A typical OCR profile for section 1.1:

Register and cycle questions. Describe the role of named registers; trace an instruction through fetch-decode-execute.
Bus reasoning. Link address-bus width to addressable memory ( $2^{n}$ ) and data-bus width to throughput.
Comparison and discussion. HDD vs SSD, RISC vs CISC, CPU vs GPU, justified against a scenario (levels of response).
OS internals. Interrupt handling steps, a scheduling trace, and paging versus segmentation versus virtual memory.

Check your knowledge

A mix of recall and applied questions covering the section. Attempt them under timed conditions, then check against the solutions.

State the role of the Memory Address Register (MAR). (1 mark)
A processor has a 24-line address bus. State the number of locations it can address. (1 mark)
Explain one reason a wider data bus can improve performance. (2 marks)
State one advantage of an SSD over a magnetic hard disk drive. (1 mark)
Explain why ROM is used to hold the bootstrap. (2 marks)
State the purpose of an interrupt service routine. (1 mark)

Solutions

Q1: The MAR holds the address of the memory location currently being read from or written to; its contents are placed on the address bus.
Q2: $2^{24} = 16\,777\,216$ locations (16 MiB if each is a byte).
Q3: A wider data bus transfers more bits per memory access, so more data moves between the processor and memory per transfer, increasing throughput.
Q4: Any one of: faster access, no moving parts (shock resistant), silent, lower power, smaller and lighter.
Q5: The bootstrap must run the instant power is applied; ROM is non-volatile and keeps its contents without power, whereas RAM is volatile and would be empty at switch-on.
Q6: It is the routine run to service a specific interrupt, dealing with the event (for example handling a key press) before the interrupted program resumes.

Sources & how we know this

OCR AS and A Level Computer Science (H046, H446) specification — OCR (2015)