How is a processor organised, and what is the difference between the Von Neumann and Harvard architectures?
Computer architecture: the components of the CPU (the ALU, the control unit, the registers and the system buses), the Von Neumann stored-program concept, and the difference between Von Neumann and Harvard architectures.
An Eduqas Component 2 answer on computer architecture: the components of the CPU (ALU, control unit, registers), the address, data and control buses, the Von Neumann stored-program concept, and how Von Neumann differs from Harvard architecture.
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What this dot point is asking
Eduqas wants you to describe the components of the CPU (the ALU, the control unit, the registers and the buses), explain the Von Neumann stored-program concept, and contrast the Von Neumann and Harvard architectures with the advantages of each.
The answer
The components of the CPU
The system buses
Von Neumann and Harvard architectures
Examples in context
Almost every general-purpose computer, from a phone to a server, is fundamentally a Von Neumann stored-program machine, which is why software can be installed and changed so freely. The Harvard architecture appears in microcontrollers and in the cache design of modern CPUs (separate instruction and data caches) precisely to ease the bottleneck. Understanding the ALU, control unit, registers and buses here is the foundation for the next dot point, the fetch-decode-execute cycle, which puts them all in motion.
Try this
Q1. State the function of the ALU. [1 mark]
- Cue. It performs arithmetic and logical operations.
Q2. Which bus is unidirectional, and what does it carry? [2 marks]
- Cue. The address bus; it carries the memory address (from the CPU to memory).
Q3. Give one advantage of the Harvard architecture over Von Neumann. [1 mark]
- Cue. Instructions and data can be fetched simultaneously (separate buses), avoiding the Von Neumann bottleneck and improving speed.
Exam-style practice questions
Practice questions written in the style of WJEC Eduqas exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.
Eduqas 20195 marksDescribe the role of the ALU, the control unit and the system buses within a processor, and state what is meant by the Von Neumann stored-program concept.Show worked answer →
ALU (up to 1 mark): the arithmetic and logic unit performs all arithmetic (addition, subtraction) and logical operations (AND, OR, comparisons).
Control unit (up to 1 mark): coordinates the operation of the processor, decoding instructions and sending control signals to direct the other components and manage the fetch-decode-execute cycle.
Buses (up to 2 marks): the address bus carries memory addresses (one way, from the CPU); the data bus carries data and instructions both ways between the CPU and memory; the control bus carries control and timing signals.
Von Neumann stored-program concept (up to 1 mark): both program instructions and data are stored together in the same main memory and travel over the same bus, so the computer can be reprogrammed by loading different instructions.
Markers reward the role of the ALU and control unit, the three buses with their directions, and the shared-memory stored-program idea.
Eduqas 20214 marksCompare the Von Neumann architecture with the Harvard architecture, giving one advantage of each.Show worked answer →
Von Neumann (up to 2 marks): instructions and data share the same memory and the same bus. Advantage: simpler and cheaper to build, and memory is used flexibly between code and data.
Harvard (up to 2 marks): instructions and data have separate memories and separate buses. Advantage: instructions and data can be fetched at the same time, improving speed and avoiding the Von Neumann bottleneck.
Markers reward the shared-memory definition of Von Neumann and the separate-memory definition of Harvard, with a valid advantage of each (Von Neumann simpler/cheaper/flexible; Harvard faster/parallel fetch).
Related dot points
- The fetch-decode-execute cycle: the special-purpose registers (PC, MAR, MDR, CIR, ACC) and their use in fetching, decoding and executing an instruction, and the effect of the cycle on the registers.
An Eduqas Component 2 answer on the fetch-decode-execute cycle: the special-purpose registers (program counter, MAR, MDR, current instruction register, accumulator) and exactly how each is used to fetch, decode and execute an instruction.
- Assembly language: the instruction set with its opcode and operand, common operations (load, store, add, jump, compare), the relationship between assembly and machine code, and immediate, direct and indirect addressing modes.
An Eduqas Component 2 answer on assembly language: the opcode and operand structure of an instruction, common operations such as load, store, add, jump and compare, how assembly maps to machine code via the assembler, and immediate, direct and indirect addressing modes.
- Processor performance: the factors affecting CPU performance (clock speed, number of cores, cache size and word length), the difference between RISC and CISC, and the use of pipelining and parallel processing.
An Eduqas Component 2 answer on processor performance: how clock speed, number of cores, cache size and word length affect speed, the difference between RISC and CISC, and how pipelining and parallel processing increase throughput.
- Input, output and storage: the role of input and output devices, the memory hierarchy from registers and cache to RAM and secondary storage, and the operating principles, advantages and uses of magnetic, optical and solid-state storage.
An Eduqas Component 2 answer on input, output and storage: the role of input and output devices, the memory hierarchy from registers and cache to RAM and secondary storage, and how magnetic, optical and solid-state (flash) storage work with their advantages and uses.
- Logical operations: the logic gates (AND, OR, NOT, NAND, NOR, XOR) and their truth tables, building and reading truth tables for expressions, the laws of Boolean algebra and De Morgan's laws, and simplifying expressions with Karnaugh maps.
An Eduqas Component 1 answer on logical operations: the six logic gates and their truth tables, building truth tables for expressions, simplifying with the laws of Boolean algebra and De Morgan's laws, and using Karnaugh maps to minimise a Boolean expression.
Sources & how we know this
- WJEC Eduqas GCE AS/A Level Computer Science specification (from 2015) — Eduqas (2015)