What does the hardware and communication part of Eduqas Component 2 cover?

It covers the components of the CPU (the ALU, control unit, registers and system buses) and the Von Neumann and Harvard architectures, the fetch-decode-execute cycle with its special-purpose registers (PC, MAR, MDR, CIR, ACC), assembly language and the immediate, direct and indirect addressing modes, the factors affecting CPU performance (clock speed, cores, cache, word length) with RISC versus CISC, pipelining and parallel processing, input and output devices and the memory hierarchy with magnetic, optical and solid-state storage, and computer networks (LANs and WANs, topologies, the client-server and peer-to-peer models, and network hardware).

What are the registers used in the fetch-decode-execute cycle?

The program counter (PC) holds the address of the next instruction; the memory address register (MAR) holds the address being accessed; the memory data register (MDR) holds the data or instruction transferred to or from that address; the current instruction register (CIR) holds the instruction being decoded; and the accumulator (ACC) holds the result of calculations performed by the ALU.

What is the difference between RISC and CISC?

RISC (reduced instruction set computer) uses a small set of simple, fixed-length instructions, each typically completing in one clock cycle, so more instructions are needed per task but each is fast and uniform, which suits pipelining. CISC (complex instruction set computer) uses a large set of complex, variable-length instructions, some taking many cycles, doing more per instruction at the cost of greater complexity.

What is the difference between a switch and a router?

A switch connects devices within a single network and forwards data only to the specific device it is addressed to, using MAC addresses. A router connects different networks together (for example a home network to the internet) and routes data packets between them using IP addresses.

How should I revise computer architecture and hardware for Eduqas?

Learn the CPU components and the three buses, then rehearse the fetch-decode-execute cycle step by step with the registers named in order, since this is examined heavily. Be able to compare the three addressing modes with a worked example, the CPU performance factors with RISC versus CISC and pipelining, the storage technologies and the memory hierarchy, and the network topologies and models with their pros and cons.

EnglandComputer Science

Eduqas A-Level Computer Science computer architecture and hardware: the CPU, fetch-execute, performance and networks made exam-ready

A deep-dive Eduqas Component 2 guide to computer architecture and hardware (specification section 3.1). Covers the CPU components and the Von Neumann and Harvard architectures, the fetch-decode-execute cycle and registers, assembly language and addressing modes, CPU performance (RISC, CISC, pipelining, parallelism), the memory hierarchy and storage, and networks with topologies and models.

Generated by Claude Opus 4.815 min readEduqas-A-Level-CS-3.1Updated 2026-06-02

Reviewed by: AI editorial process; not yet individually human-reviewed

Jump to a section

What this section actually demands
The processor
Performance, storage and networks
How this section is examined
Check your knowledge

What this section actually demands

The hardware and communication part of Component 2 (specification section 3.1) is the architecture core of the course: how a processor is built, how it executes instructions, what makes it fast, how data is stored, and how computers are networked. Eduqas rewards precise, ordered explanations, especially of the fetch-decode-execute cycle, and clear comparisons (Von Neumann versus Harvard, RISC versus CISC, the topologies and models).

This guide walks through the topics in order and sets out the exam patterns Eduqas repeats. Each topic has a matching dot-point page with practice; this overview ties them together.

The processor

Computer architecture covers the ALU, control unit, registers and the three system buses (address, data, control), plus the Von Neumann stored-program concept and how it differs from Harvard. The fetch-decode-execute cycle puts these in motion using the special-purpose registers (PC, MAR, MDR, CIR, ACC), and is the single most examined process in this section. Assembly language is the human-readable view of machine code: opcode and operand, common operations, and the immediate, direct and indirect addressing modes.

Performance, storage and networks

Processor performance covers clock speed, cores, cache and word length, RISC versus CISC, pipelining and parallel processing. Input, output and storage covers the input and output devices, the memory hierarchy (registers, cache, RAM, secondary storage), and magnetic, optical and solid-state storage. Networks covers LANs and WANs, the bus, star and mesh topologies, the client-server and peer-to-peer models, and the hardware (NICs, switches, routers).

How this section is examined

A typical Eduqas profile for section 3.1:

Architecture. Describe the CPU components and buses; compare Von Neumann and Harvard.
Fetch-execute. Describe the cycle step by step with the registers named; explain the PC for normal versus jump instructions.
Assembly. Explain opcode and operand and the three addressing modes with an example.
Performance, storage, networks. Explain the performance factors and RISC/CISC/pipelining; compare storage technologies and the memory hierarchy; describe topologies and the client-server/peer-to-peer models.

Check your knowledge

A mix of recall and applied questions covering the section. Attempt them under timed conditions, then check against the solutions.

State the function of the control unit. (1 mark)
Which register holds the address of the next instruction? (1 mark)
In direct addressing, what does the operand represent? (1 mark)
Give one factor (other than clock speed) that affects CPU performance. (1 mark)
Name the levels of the memory hierarchy in order of decreasing speed. (2 marks)
State one difference between a switch and a router. (2 marks)

Sources & how we know this

WJEC Eduqas GCE AS/A Level Computer Science specification (from 2015) — Eduqas (2015)