What determines how fast a processor is, and how do RISC, CISC, multiple cores and pipelining improve performance?
Processor performance: the factors affecting CPU performance (clock speed, number of cores, cache size and word length), the difference between RISC and CISC, and the use of pipelining and parallel processing.
An Eduqas Component 2 answer on processor performance: how clock speed, number of cores, cache size and word length affect speed, the difference between RISC and CISC, and how pipelining and parallel processing increase throughput.
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What this dot point is asking
Eduqas wants you to explain the factors affecting CPU performance (clock speed, cores, cache, word length), distinguish RISC from CISC, and explain pipelining and parallel processing, including why RISC suits pipelining.
The answer
Factors affecting CPU performance
RISC and CISC
Pipelining and parallel processing
Examples in context
This dot point explains real buying decisions: a gaming or editing machine values cores and cache, while some single-threaded workloads value clock speed. ARM (RISC) chips power virtually every smartphone because their simplicity gives excellent performance per watt, while desktop x86 (CISC) chips internally translate to RISC-like operations and pipeline heavily. Pipelining and multiple cores are how the basic fetch-decode-execute cycle is made to deliver billions of instructions per second, connecting this topic directly to the previous two.
Try this
Q1. State how clock speed affects CPU performance. [1 mark]
- Cue. It is the number of cycles per second, so a higher clock speed executes more instructions per second (faster processing).
Q2. Give one difference between RISC and CISC. [1 mark]
- Cue. RISC uses a small set of simple, uniform, single-cycle instructions; CISC uses a large set of complex, variable-length instructions.
Q3. Explain how pipelining increases throughput. [2 marks]
- Cue. It overlaps the fetch, decode and execute stages, so while one instruction executes, the next is decoded and a third fetched, producing a result every cycle.
Exam-style practice questions
Practice questions written in the style of WJEC Eduqas exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.
Eduqas 20206 marksExplain how clock speed, the number of cores and cache size each affect the performance of a CPU.Show worked answer →
Clock speed (up to 2 marks): the clock speed (measured in GHz) is the number of fetch-decode-execute cycles per second; a higher clock speed means more instructions executed per second, so faster processing, though it also generates more heat.
Number of cores (up to 2 marks): each core is an independent processing unit, so a multi-core CPU can execute several instructions or threads truly simultaneously; this speeds up tasks that can be split (parallelised), but a task that cannot be divided gains little.
Cache size (up to 2 marks): cache is small, very fast memory close to the CPU holding frequently used data and instructions; a larger cache means more accesses are served quickly without waiting for slower main memory, reducing delays.
Markers reward cycles-per-second for clock speed, simultaneous execution for cores (with the parallelisable caveat), and faster access avoiding main memory for cache.
Eduqas 20225 marksCompare RISC and CISC processor designs, and explain how pipelining improves performance and why RISC is better suited to it.Show worked answer →
RISC versus CISC (up to 3 marks): RISC (reduced instruction set computer) uses a small set of simple, fixed-length instructions, each typically executing in one clock cycle; CISC (complex instruction set computer) uses a large set of more complex, variable-length instructions, some taking many cycles. RISC needs more instructions for a task but each is fast and uniform; CISC does more per instruction but is more complex.
Pipelining (up to 2 marks): pipelining overlaps the stages of the fetch-decode-execute cycle so that while one instruction is being executed, the next is decoded and a third is fetched, increasing throughput. RISC suits pipelining because its uniform, single-cycle instructions fill the pipeline stages evenly without stalls.
Markers reward the simple-uniform versus complex-variable distinction and the overlapping-stages explanation of pipelining with the RISC suitability point.
Related dot points
- Computer architecture: the components of the CPU (the ALU, the control unit, the registers and the system buses), the Von Neumann stored-program concept, and the difference between Von Neumann and Harvard architectures.
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Sources & how we know this
- WJEC Eduqas GCE AS/A Level Computer Science specification (from 2015) — Eduqas (2015)