How does the processor fetch, decode and execute an instruction, and what role does each register play?
The fetch-decode-execute cycle: the special-purpose registers (PC, MAR, MDR, CIR, ACC) and their use in fetching, decoding and executing an instruction, and the effect of the cycle on the registers.
An Eduqas Component 2 answer on the fetch-decode-execute cycle: the special-purpose registers (program counter, MAR, MDR, current instruction register, accumulator) and exactly how each is used to fetch, decode and execute an instruction.
Reviewed by: AI editorial process; not yet individually human-reviewed
Have a quick question? Jump to the Q&A page
Jump to a section
What this dot point is asking
Eduqas wants you to describe the fetch-decode-execute cycle step by step, name the special-purpose registers (PC, MAR, MDR, CIR, ACC) and state exactly how each is used, and explain how the program counter behaves for a normal instruction versus a jump.
The answer
The special-purpose registers
The fetch stage
Decode and execute
Examples in context
Every instruction your computer runs, billions per second, goes through this exact cycle, and the clock speed is simply how many cycles run per second. The registers here are what the assembly language in the next dot point manipulates directly (LOAD, STORE, ADD operate on the accumulator and memory via these registers). Pipelining and multiple cores (covered under performance) are clever ways of overlapping or duplicating this cycle to do more per second.
Try this
Q1. What does the program counter (PC) hold? [1 mark]
- Cue. The address of the next instruction to be fetched.
Q2. During fetch, the contents of the PC are first copied into which register? [1 mark]
- Cue. The memory address register (MAR).
Q3. What happens to the PC when a jump (branch) instruction executes? [2 marks]
- Cue. It is overwritten with the target address (rather than just incremented), so execution continues from there.
Exam-style practice questions
Practice questions written in the style of WJEC Eduqas exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.
Eduqas 20206 marksDescribe the fetch stage of the fetch-decode-execute cycle, naming each register involved and stating what it does.Show worked answer →
Award up to 6 marks for a correct sequence with the registers named:
The address of the next instruction is held in the program counter (PC); it is copied into the memory address register (MAR).
The PC is then incremented so it points to the following instruction.
The address in the MAR is placed on the address bus, and a read signal is sent; the instruction at that address is fetched from memory.
The fetched instruction travels on the data bus into the memory data register (MDR).
The instruction is then copied from the MDR into the current instruction register (CIR), ready to be decoded.
Markers reward the PC-to-MAR copy, incrementing the PC, the memory read via the address/data buses, and the MDR-to-CIR transfer. The order matters.
Eduqas 20224 marksState the purpose of the program counter (PC), the current instruction register (CIR) and the accumulator (ACC), and explain what happens to the PC during a normal instruction and during a jump.Show worked answer →
Purposes (up to 3 marks, one each): the PC holds the address of the next instruction to be fetched; the CIR holds the instruction currently being decoded and executed; the accumulator (ACC) holds the result of calculations performed by the ALU.
The PC during instructions (up to 1 mark): for a normal instruction the PC is simply incremented to point to the next instruction; for a jump (branch) instruction the PC is overwritten with the target address, so execution continues from there.
Markers reward the three register purposes and the increment-versus-overwrite behaviour of the PC for normal versus jump instructions.
Related dot points
- Computer architecture: the components of the CPU (the ALU, the control unit, the registers and the system buses), the Von Neumann stored-program concept, and the difference between Von Neumann and Harvard architectures.
An Eduqas Component 2 answer on computer architecture: the components of the CPU (ALU, control unit, registers), the address, data and control buses, the Von Neumann stored-program concept, and how Von Neumann differs from Harvard architecture.
- Assembly language: the instruction set with its opcode and operand, common operations (load, store, add, jump, compare), the relationship between assembly and machine code, and immediate, direct and indirect addressing modes.
An Eduqas Component 2 answer on assembly language: the opcode and operand structure of an instruction, common operations such as load, store, add, jump and compare, how assembly maps to machine code via the assembler, and immediate, direct and indirect addressing modes.
- Processor performance: the factors affecting CPU performance (clock speed, number of cores, cache size and word length), the difference between RISC and CISC, and the use of pipelining and parallel processing.
An Eduqas Component 2 answer on processor performance: how clock speed, number of cores, cache size and word length affect speed, the difference between RISC and CISC, and how pipelining and parallel processing increase throughput.
- Input, output and storage: the role of input and output devices, the memory hierarchy from registers and cache to RAM and secondary storage, and the operating principles, advantages and uses of magnetic, optical and solid-state storage.
An Eduqas Component 2 answer on input, output and storage: the role of input and output devices, the memory hierarchy from registers and cache to RAM and secondary storage, and how magnetic, optical and solid-state (flash) storage work with their advantages and uses.
- Memory management: how the operating system allocates and protects memory between processes, paging and segmentation, and virtual memory using secondary storage to extend the apparent size of main memory.
An Eduqas Component 2 answer on memory management: how the operating system allocates and protects memory between processes, the difference between paging and segmentation, and how virtual memory uses secondary storage to extend the apparent size of main memory.
Sources & how we know this
- WJEC Eduqas GCE AS/A Level Computer Science specification (from 2015) — Eduqas (2015)