Understand the components of the processor (ALU, control unit, registers), the fetch-decode-execute cycle, the role of each register, and the factors affecting processor performance.

The address of the next instruction held in the program counter (PC) is copied into the memory address register (MAR). A read signal is sent on the control bus, and the instruction at that address is fetched from main memory along the data bus into the memory data register (MDR). The instruction is then copied from the MDR into the current instruction register (CIR), ready to be decoded. At some point during the fetch the program counter is incremented so that it points to the next instruction in sequence.

Markers reward the PC to MAR transfer, the read from memory into the MDR, the copy into the CIR, and incrementing the PC (which is allowed before the instruction is decoded). Naming each register correctly is the key to full marks.

Clock speed is the number of cycles per second; a higher clock speed means the processor steps through the fetch-decode-execute cycle more times per second, so it executes more instructions per second. Increasing the number of cores lets the processor execute several instructions truly in parallel, raising throughput when work can be divided among the cores.

Doubling the cores does not always double performance because not all tasks can be split into independent parts that run in parallel; a task that is inherently sequential, or parts that must wait for shared data, cannot use the extra cores, so the speed-up is limited by the portion that must run serially.

Markers reward the cycles-per-second effect of clock speed, the parallelism of multiple cores, and the explanation that only parallelisable work benefits from extra cores.