Understand the internal components of a computer, the role of the processor, main memory and buses, and the difference between RAM, ROM and cache memory.

A focused answer to AQA A-Level Computer Science 4.7.1, covering the internal components of a computer, the role of the processor, main memory and the system buses, and the differences between RAM, ROM and cache memory.

Generated by Claude Opus 4.88 min answerUpdated 2026-06-02

Reviewed by: AI editorial process; not yet individually human-reviewed

Have a quick question? Jump to the Q&A page

Jump to a section

What this dot point is asking
The main internal components
The system buses
RAM, ROM and cache

What this dot point is asking

AQA wants you to identify the main internal components of a computer, explain the roles of the processor, main memory and the system buses, and distinguish RAM, ROM and cache memory.

The main internal components

These components reflect the stored program design: the processor and main memory are the two halves that the buses connect, with the program and its data living together in memory and being fetched into the processor to be executed. Holding this overall picture in mind makes the role of each piece clearer, because every part exists to move instructions and data between memory and the processor as efficiently as possible.

The system buses

The width of each bus directly affects performance and capacity. A wider address bus can address more memory ( $2^n$ locations), and a wider data bus moves more bits per transfer, so doubling the data bus width roughly doubles the data moved per cycle. This is why bus width appears in the list of factors affecting processor performance, and why exam questions frequently ask you to calculate addressable memory from the number of address lines.

RAM, ROM and cache

Cache exists because of a speed mismatch: the processor is far faster than main memory, so without cache it would spend much of its time idle, waiting. By keeping recently used data close to the processor in a small, fast store, cache lets most accesses be served quickly, with only the occasional miss requiring a slower trip to main memory. This memory hierarchy (registers, then cache, then RAM, then secondary storage) trades speed against capacity and cost at each level, which is a central idea in how real machines are organised.

Calculate addressable memory and data width from bus widths

Target: for an address bus of 20 lines and a data bus of 16 lines, find the addressable memory and the largest value per transfer.

step 1: Addressable locations from the address bus

With 20 address lines the number of distinct addresses is $2^{20} = 1\,048\,576$ , which is 1 mebibyte of locations if each is one byte.

step 2: Data per transfer from the data bus

With 16 data lines, 16 bits (2 bytes) move in one transfer, with a largest unsigned value of $2^{16} - 1 = 65\,535$ .

step 3: Effect of widening the address bus

Adding one more address line gives $2^{21}$ , doubling the addressable memory to 2 mebibytes of locations, because each extra line doubles the count.

step 4: State the results

The system can address $1\,048\,576$ locations and transfer 16 bits at a time; each extra address line doubles the addressable memory, which is the key relationship examiners test.

Exam-style practice questions

Practice questions written in the style of AQA exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.

AQA 20194 marksA computer has an address bus of 16 lines and a data bus of 8 lines. Calculate the maximum number of memory locations that can be addressed and the largest value that can be transferred in a single bus cycle, and explain how widening the address bus would change the addressable memory.

Show worked answer →

The address bus has 16 lines, so it can address $2^{16} = 65\,536$ memory locations.

The data bus has 8 lines, so it can transfer an 8-bit value in one cycle, with a largest unsigned value of $2^8 - 1 = 255$ .

Widening the address bus increases the addressable memory because each extra line doubles the number of distinct addresses ( $2^n$ for $n$ lines), so a 17-line bus would address $2^{17} = 131\,072$ locations, twice as many.

Markers reward $2^{16} = 65\,536$ for the addresses, 255 (or 8-bit) for the data, and the doubling relationship for each extra address line.

AQA 20214 marksExplain the difference between RAM, ROM and cache memory, stating one purpose of each.

Show worked answer →

RAM (random access memory) is volatile working memory that can be read and written; it holds the programs and data currently in use and loses its contents when power is removed. Its purpose is to provide fast, changeable storage for running software.

ROM (read-only memory) is non-volatile and retains its contents without power; its purpose is to hold the boot firmware (such as the BIOS) that starts the computer.

Cache is small, very fast memory on or near the processor; its purpose is to store frequently or recently used instructions and data so the processor waits less for the slower main memory.

Markers reward the volatile-versus-non-volatile distinction, identifying cache as the small fast store near the CPU, and a valid purpose for each.

Related dot points

Sources & how we know this

AQA A-level Computer Science (7517) specification — AQA (2015)