How do flip-flops store a bit, and how are they used to build counters and registers?
Sequential logic and flip-flops: the difference between combinational and sequential logic, the SR latch, D-type and JK flip-flops, clocking, and using flip-flops to build counters and shift registers.
A focused answer to WJEC A-Level Electronics sequential logic, covering the difference between combinational and sequential logic, the SR latch, D-type and JK flip-flops, clocking and edge triggering, and how flip-flops are connected to make counters and shift registers.
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What this dot point is asking
Sequential logic is where digital circuits gain memory. WJEC expects you to distinguish combinational from sequential logic, describe the SR latch, the D-type and the JK flip-flop, understand clocking and edge triggering, and connect flip-flops to build counters and shift registers. The toggling JK flip-flop and the divide-by-N counter are reliable, high-mark exam questions.
The answer
Combinational versus sequential
The SR latch and the clock
The simplest memory is the SR latch, made from two cross-coupled NAND or NOR gates: a pulse on Set makes the output high, a pulse on Reset makes it low, and it holds its state in between. To keep many circuits in step, flip-flops are clocked: they only change state on the rising (or falling) edge of a clock pulse, which is called edge triggering.
The D-type and JK flip-flops
The toggle mode is the key to counting: a flip-flop that flips on every clock edge produces one output cycle for every two input cycles, dividing the frequency by two.
Counters and shift registers
Examples in context
- Example 1. A digital clock's seconds counter
- A divide-by-sixty counter, built from chained flip-flops with decoding logic, turns a one-hertz tick into a count that rolls over each minute. The sequential design is essential because the display must remember how many seconds have elapsed, which combinational logic alone cannot do.
- Example 2. Serial data into a parallel display
- A shift register clocks bits in one at a time from a serial line, and once full, all its stored bits are read out in parallel to drive a display. This serial-to-parallel conversion, used in LED matrices and communication links, relies on each D-type passing its bit to the next on every clock edge.
- Example 3. Frequency division for timing
- A high-frequency oscillator divided down by a chain of toggling flip-flops yields slower, accurate timing signals from one crystal. A 32768 Hz watch crystal divided by gives exactly one pulse per second, which is how quartz watches keep time.
Try this
Q1. State the output behaviour of a JK flip-flop when J = 1 and K = 1, and what is fed to it to make a counter. [2 marks]
- Cue. It toggles (changes state) on each clock edge; a clock signal is fed to it, and stages are chained for a counter.
Q2. A binary counter has five flip-flop stages. By what factor does it divide the input frequency? [1 mark]
- Cue. .
Exam-style practice questions
Practice questions written in the style of WJEC exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.
WJEC Eduqas 20205 marksA JK flip-flop has both J and K tied high and is fed with a clock signal. State the output behaviour, and explain how four such flip-flops connected in series form a divide-by-sixteen counter.Show worked answer →
With J = K = 1 a JK flip-flop toggles: on each active clock edge its output changes state.
So one toggling flip-flop's output completes one cycle for every two input clock pulses, dividing the frequency by two.
Connecting four in series, with each flip-flop's output clocking the next, divides the frequency by two at each stage: 2 then 4 then 8 then 16. After four stages the overall division is , so the final output completes one cycle for every sixteen input pulses, and the four outputs read the count in binary from 0 to 15.
Markers reward the toggle behaviour, the divide-by-two per stage, and the overall divide-by-sixteen with the binary count.
WJEC Eduqas 20183 marksExplain the difference between combinational and sequential logic, giving an example of each.Show worked answer →
Combinational logic has an output that depends only on the present combination of inputs, with no memory of past inputs. An example is a logic gate or an adder.
Sequential logic has an output that depends on the present inputs and on the stored state (the past), because it contains memory elements such as flip-flops. An example is a counter or a shift register.
The key distinction is memory: sequential circuits remember, combinational circuits do not.
Markers reward the no-memory versus memory distinction and one valid example of each.
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Sources & how we know this
- WJEC Eduqas GCE A-level Electronics specification — WJEC Eduqas (2017)