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EnglandComputer ScienceQuick questions
1.1 Systems architecture
Quick questions on CPU architecture and the fetch-decode-execute cycle - OCR GCSE Computer Science J277
3short Q&A pairs drawn directly from our worked dot-point answer. For full context and worked exam questions, read the parent dot-point page.
What is q1?Show answer
Name the three stages of the fetch-decode-execute cycle in order. [3 marks]
What is q2?Show answer
State which register holds the address of the next instruction to be fetched. [1 mark]
What is q3?Show answer
State one feature of the von Neumann architecture. [1 mark]
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