How do flip-flops store a bit, and how are they combined into counters?
Sequential logic: the bistable/flip-flop (set-reset, D and JK), latching, and binary counters and frequency division.
A CCEA A-Level Technology and Design answer on sequential logic, the set-reset, D and JK flip-flops as one-bit memory and latches, and how flip-flops are chained into binary counters and frequency dividers.
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What this dot point is asking
CCEA expects you to distinguish combinational from sequential logic, to describe the flip-flop (bistable) in its SR, D and JK forms as one-bit memory and a latch, and to explain how flip-flops are chained into binary counters and frequency dividers. Frequency-division calculations are common.
The answer
Combinational vs sequential logic
Types of flip-flop
Counters and frequency division
Worked example: a counter as a divider and timer
Examples in context
Example 1. Digital clock. A crystal oscillator's high frequency is divided down by a chain of counters to one pulse per second, the divide-by- principle producing timekeeping.
Example 2. Latching emergency stop. A momentary press latches an SR flip-flop that holds the machine off until a deliberate reset, using memory so a brief press has a lasting effect.
Try this
Q1. State the difference between combinational and sequential logic in one sentence. [2 marks]
- Cue. Combinational output depends only on the present inputs (no memory); sequential output depends on present inputs and the previous stored state (has memory).
Q2. By what factor does a single toggling flip-flop divide an input frequency? [1 mark]
- Cue. By two.
Q3. A 3-bit binary counter is clocked at 8 Hz. Find the frequency at the third flip-flop output. [2 marks]
- Cue. Division , so .
Exam-style practice questions
Practice questions written in the style of CCEA exam questions on this dot point, with worked answer explainers. The year tag is the paper they imitate, not the source.
CCEA 20196 marksExplain the difference between combinational and sequential logic, and describe how a set-reset (SR) latch can be used to remember that an event has occurred.Show worked answer →
Combinational logic produces an output that depends only on the present inputs (for example AND, OR gate networks); it has no memory. Sequential logic produces an output that depends on the present inputs and on the previous state, so it can store information (remember). The basic sequential element is the flip-flop (bistable).
A set-reset (SR) latch (made from two cross-coupled NAND or NOR gates) has two inputs, Set and Reset, and an output Q. Pulsing Set makes and it stays at 1 (latched) even after Set returns low; pulsing Reset makes and it stays there. So a momentary event (a sensor pulse) can be remembered: for example a fault sensor briefly pulses Set, latching an alarm on until an operator presses Reset.
Markers reward the present-inputs-only (combinational, no memory) vs present-plus-previous-state (sequential, has memory) contrast, and a correct description of the SR latch holding its output after a momentary set, with reset to clear.
CCEA 20214 marksA 4-bit binary counter is driven by a 16 Hz clock. State the frequency at the output of the fourth (most significant) flip-flop, and explain why.Show worked answer →
Each flip-flop in a binary (ripple) counter divides the frequency by two (it toggles once for every two input pulses). With four stages the overall division is .
So the output of the fourth flip-flop has frequency:
Each successive flip-flop halves the frequency: 16 Hz to 8 Hz (after stage 1), to 4 Hz (stage 2), to 2 Hz (stage 3), to 1 Hz (stage 4). A counter therefore doubles as a frequency divider.
Markers want the divide-by-two-per-stage idea, overall, and the correct 1 Hz output.
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Sources & how we know this
- CCEA GCE Technology and Design specification — CCEA (2016)