Describe computer architecture in depth: processor design, parallel processing, peripherals, and the hardware and methods of communication.

What this dot point is asking

WJEC wants you to describe modern computer architecture in depth: processor design and the role of buses and registers, parallel processing, peripherals and storage, and the hardware and methods of communication. This is the architecture strand of Unit 4 and extends the AS hardware topic. Expect questions on buses (especially address-bus width and addressable memory) and on parallel processing, which reward precise, quantitative answers.

The answer

Processor architecture and buses

Bus width directly limits the machine: a wider data bus moves more bits at once, and a wider address bus can address more memory, so architecture decisions are quantitative, not just descriptive.

Address-bus width and addressable memory

This relationship is a favourite calculation: given the address-bus width you can state the maximum memory, and given a memory size you can state the address-bus width needed.

Parallel processing

Parallel processing uses multiple processors or cores to carry out several computations at once, so a task finishes faster. It gives a large speed-up for problems that divide into independent parts (such as processing each pixel of an image) but little benefit for inherently sequential problems where each step depends on the previous result.

Peripherals, storage and communication

Peripherals (input, output and storage devices) attach through interfaces and controllers, and communication hardware (switches, routers, network interface cards) with serial or parallel methods moves data between machines.

Examples in context

Example 1. Why a GPU renders graphics fast

A graphics processor has thousands of small cores, ideal for the highly parallel task of computing each pixel independently. The same architecture would help little with a strictly sequential calculation, which is exactly why GPUs excel at graphics and machine learning but are not a universal speed-up, illustrating the parallel-processing trade-off.

Example 2. Address-bus width as a historical limit

Early 32-bit machines could address only about four gigabytes because a 32-line address bus reaches 2 to the power 32 locations. Moving to 64-bit addressing lifted this limit enormously. This shows the address-bus formula is not abstract: it set a real ceiling on usable memory that drove the move to 64-bit machines.

Example 3. Buses as a shared bottleneck

When the processor, memory and a fast disk all share the same bus, heavy traffic from one can slow the others, just as one busy road slows all the cars on it. Recognising the bus as a shared, finite resource explains why bus width and dedicated channels matter for performance, a point examiners reward.

Try this

Q1. State how many memory locations a 16-line address bus can address. [1 mark]

• Cue. 2 to the power 16 = 65,536 locations.

Q2. State one characteristic of a problem that makes it well suited to parallel processing. [1 mark]

• Cue. It divides into independent parts that can be computed at the same time with little coordination.