What does the Eduqas combinational logic module cover?

It covers the logic gates (AND, OR, NOT, NAND, NOR and XOR) with their symbols and truth tables and the meaning of logic high and low; Boolean algebra (writing expressions, the laws, De Morgan's laws and simplifying to fewer gates); designing combinational circuits from a word description or truth table, combining gates, and the universal NAND and NOR gates; and binary arithmetic with the half adder (sum and carry) and full adder (with a carry in) chained to add multi-bit numbers.

Which results recur most across this module?

The gate truth tables, the laws of Boolean algebra and De Morgan's two laws ($\overline{A + B} = \overline{A} \cdot \overline{B}$ and $\overline{A \cdot B} = \overline{A} + \overline{B}$), the half-adder outputs ($S = A \oplus B$, $C = A \cdot B$), and binary place values as powers of two. There is little numerical calculation, but plenty of truth-table and algebra work that must be shown.

What is the most common mistake in this module?

Confusing similar gates and applying De Morgan's halfway. Frequent slips are mixing up OR with XOR (XOR is 1 only when the inputs differ), mixing up NAND and NOR, breaking the bar in De Morgan's without swapping the operator (or vice versa), forgetting to name the laws used in a simplification, and forgetting the carry when $1 + 1 = 10_2$ in a half adder.

Why does simplifying a logic circuit matter?

Each gate costs money, takes space, adds a small delay and uses power, so an equivalent circuit with fewer gates is cheaper, faster and more reliable. Boolean algebra and De Morgan's laws let you reduce an expression, and the universal NAND gate lets a whole design be built from one chip type. Simplification is therefore a real engineering benefit, not just an exam exercise.

How should I revise combinational logic?

Memorise the six gate truth tables until instant. Practise writing Boolean expressions from circuits and from word descriptions, then simplifying them with the named laws and De Morgan's. Drill designing a circuit from a truth table (a term per 1-row, then OR them) and building gates from NAND only. Finally, master binary counting and the half-adder and full-adder outputs, and add multi-bit numbers by rippling the carry.

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Eduqas GCSE Electronics: combinational logic (gates, truth tables, Boolean algebra, circuit design, adders)

A deep-dive Eduqas GCSE Electronics guide to the combinational logic module within Component 1. Covers the logic gates and their truth tables, Boolean algebra and De Morgan's laws, designing combinational circuits from a description or truth table with universal NAND and NOR gates, and binary adders (the half adder and full adder).

Generated by Claude Opus 4.813 min readC490 Component 1Updated 2026-06-02

Reviewed by: AI editorial process; not yet individually human-reviewed

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What this module actually demands
Gates and Boolean algebra
Design and arithmetic
How this module is examined
Check your knowledge

What this module actually demands

Combinational logic is the digital heart of Component 1. It moves from analogue voltages to circuits that work purely with logic 0s and 1s, where the output depends only on the present inputs. It covers the six gates and their truth tables, the Boolean algebra used to write and simplify circuits, the method for designing a circuit from requirements, and the binary adders that turn gates into arithmetic. The examiners reward perfect truth tables, simplifications with each law named, sound circuit designs, and clear binary working including carries.

This guide walks through the topics in order and sets out the exam patterns Eduqas repeats. Each topic has a matching dot-point page with practice; this overview ties them together.

Gates and Boolean algebra

Logic gates and truth tables introduce AND, OR, NOT, NAND, NOR and XOR, their symbols and truth tables, and the meaning of logic high and low. Boolean algebra and De Morgan's laws write expressions ( $\cdot$ for AND, $+$ for OR, a bar for NOT), apply the laws (identity, complement, idempotent, absorption, distributive) and De Morgan's two laws, and simplify to reduce the gate count.

Design and arithmetic

Designing combinational logic turns a word description or truth table into a Boolean expression and a gate circuit, combines gates, and uses the universal NAND and NOR gates to build any function from one type. Adders and arithmetic circuits count in binary, build the half adder ( $S = A \oplus B$ , $C = A \cdot B$ ), extend it to the full adder with a carry in, and chain full adders into a ripple-carry adder for multi-bit numbers.

How this module is examined

A typical Eduqas profile for this content:

Truth tables. Completing tables for single gates and small gate networks.
Boolean algebra. Writing expressions from circuits or descriptions, applying De Morgan's, and simplifying with each law named.
Circuit design. Building a circuit from a truth table or requirements, and constructing gates from NAND only.
Binary arithmetic. Converting binary to decimal, the half-adder and full-adder outputs, and adding multi-bit numbers with carries.

Check your knowledge

A mix of recall and reasoning questions covering the module. Attempt them under timed conditions, then check against the solutions.

State when a two-input NAND gate outputs 0. (1 mark)
Give the output of a two-input XOR gate for inputs $1,1$ . (1 mark)
Apply De Morgan's law to $\overline{A \cdot B}$ . (1 mark)
Simplify $A \cdot B + A \cdot \overline{B}$ , naming the laws. (3 marks)
State the sum and carry of a half adder for $A = 1$ , $B = 1$ . (2 marks)
Convert $1010_2$ to decimal. (1 mark)

Solutions

Step 1: Q1 - NAND gate output of 0

A NAND gate is the inverse of AND. An AND gate outputs 1 only when all inputs are 1, so its inverse (NAND) outputs 0 only in that case:

A NAND outputs 0 only when both inputs are 1.

Step 2: Q2 - XOR gate with inputs 1, 1

XOR (exclusive OR) outputs 1 only when the inputs differ. When both inputs are the same (both 1 here), the output is 0:

Answer: 0.

Step 3: Q3 - De Morgan's law

De Morgan's first law states that the complement of a product equals the OR of the complements. Break the bar and swap the operator:

\overline{A \cdot B} = \overline{A} + \overline{B}

Step 4: Q4 - Boolean simplification

Apply named laws step by step. First factor out the common term, then simplify using complement and identity:

$A \cdot B + A \cdot \overline{B} = A \cdot (B + \overline{B})$ (distributive law) $= A \cdot 1$ (complement law) $= A$ (identity law).

Step 5: Q5 - half adder for inputs 1 and 1

In binary, $1 + 1 = 10_2$ , giving a sum bit of 0 and a carry bit of 1. This is exactly what the half adder implements with $S = A \oplus B$ and $C = A \cdot B$ :

Sum $= 0$ , carry $= 1$ .

Step 6: Q6 - binary to decimal conversion

Write out the binary place values from right to left as powers of two: $8, 4, 2, 1$ . Multiply each bit by its place value and add:

8 \times 1 + 4 \times 0 + 2 \times 1 + 1 \times 0 = 8 + 0 + 2 + 0 = 10

Sources & how we know this

WJEC Eduqas GCSE (9-1) Electronics specification (C490) — WJEC Eduqas (2017)